Fault Recovery for Reconfigurable Systems

Most evolutionary approaches to fault recovery in Field Programmable Gate Arrays (FPGAs) focus solely on evolving logic, as opposed to evolving both logic and routing. Since the majority of transistors in a typical FPGA are dedicated to interconnects (approximately 80% in one estimate), evolutionary fault-recovery systems should benefit by accommodating routing as well.

We are currently conducting research into an evolutionary fault-recovery system employing a genetic representation that takes into account both logic and routing configurations. Experiments were conducted using a software model of the Xilinx Virtex FPGA. Using four Virtex combinational logic blocks, we were able to evolve a 100% accurate quadrature decoder finite state machine in the presence of a stuckat-zero fault.

Evolved configuration showing routing, LUT contents, and simulated fault. Inputs are on the lines labeled MSB and LSB, referring to the least/most significant bit of the input. Wires that are shown crossing perpendicularly (eg, +) are unconnected - only wires that have > junctions are connected.